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INTEGRATED CIRCUITS
DATA SHEET
SAA4981 Monolithic integrated 16 : 9 compressor
Preliminary specification Supersedes data of May 1994 File under Integrated Circuits, IC02 1995 Oct 05
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
FEATURES * Fixed horizontal compression by a factor of video standards * 5 MHz bandwidth * Bypass function * Inputs for luminance and chrominance of side panels * Standard video inputs and outputs (Y, (B-Y) and (R-Y)) * Horizontal and vertical sync signals are not processed * Pre filters and post filters on chip. GENERAL DESCRIPTION The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 43 from, for example, 52 s to 39 s. This is necessary to display 4:3 video software on a 16 : 9 tube in the correct proportion. The capacitively coupled video inputs are Y, (B-Y) and (R-Y).
4 3
SAA4981
for most
* Three fixed screen positions (left, centre and right)
The synchronisation input HREF is a line frequency reference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, (B-Y) and (R-Y) and provides the following two possibilities: 1. Bypass function (the input signal is not compressed) 2. Compressed video by a factor of 43 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE. The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. The internal clock generation is achieved with a 54 MHz horizontal PLL which is synchronized to the positive edge of the HREF signal. The function of the IC is controlled by the three control signals CTRL1, CTRL2 and CTRL3.
QUICK REFERENCE DATA Voltages for video signals are peak-to-peak values for 75% colour bars. All voltages are referenced to VEEA = VEED = 0 V. SYMBOL VCCA VCCD ViY(p-p) ViU(p-p) ViV(p-p) ViHREF VoY(p-p) VoU(p-p) VoV(p-p) PARAMETER analog supply voltage digital supply voltage Y input voltage (peak-to-peak value) (B-Y) input voltage (peak-to-peak value) (R-Y) input voltage (peak-to-peak value) input HREF top pulse YOUT output voltage (peak-to-peak value) (B-Y)OUT output voltage (peak-to-peak value) (R-Y)OUT output voltage (peak-to-peak value) MIN. 4.75 4.75 - - - 3.0 - - - TYP. 5.0 5.0 0.32 1.33 1.05 - 0.32 1.33 1.05 MAX. 5.5 5.5 0.45 1.9 1.5 6.5 0.5 2.1 1.7 V V V V V V V V V UNIT
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA4981 SAA4981T DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT101-1 SOT137-1
1995 Oct 05
2
CTRL1
CTRL3
handbook, full pagewidth
1995 Oct 05
23 YIN CLAMP 5 MHz LOW-PASS FILTER 22 (B-Y)IN CLAMP 5 MHz LOW-PASS FILTER
BLOCK DIAGRAM
Philips Semiconductors
Monolithic integrated 16 : 9 compressor
VCCA
VEEA
VCCD
VEED
SUB
20
19
8
7
4
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER
MUX Y
18
YOUT
SAA4981
C1 C2 C3
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER
MUX BY
17
(B-Y)OUT
C1
C2
C3
3
21 (R-Y)IN CLAMP 5 MHz LOW-PASS FILTER HREF 6 HORIZONTAL SEPARATION C1 CONTROLLER 54 MHz PLL C2 C3 12 TEST 9 10 CTRL2 11
SC LINE MEMORY
SC LINE MEMORY
MUX SC LINE MEMORIES
6.7 MHz LOW-PASS FILTER MUX RY
16
(R-Y)OUT
3
C1
C2
C3
3 CLAMP REFERENCE
1
2
3
24
5
15
14
13
MHA277
Preliminary specification
BYSIDE RYSIDE YSIDE CLMY CLMBY CLMRY CLAOUT BGREF
SAA4981
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
PINNING SYMBOL CLMY CLMBY CLMRY SUB CLAOUT HREF VEED VCCD CTRL1 CTRL2 CTRL3 TEST RYSIDE BYSIDE YSIDE (R-Y)OUT (B-Y)OUT YOUT VEEA VCCA (R-Y)IN (B-Y)IN YIN BGREF PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION decoupling capacitor for Y reference voltage decoupling capacitor for BY reference voltage decoupling capacitor for RY reference voltage substrate connection (see Fig.5) internal clamping reference voltage output horizontal reference input ground for digital section positive digital supply voltage control input 1 control input 2 control input 3 test mode activation side panel input for RY side panel input for BY side panel input for Y output signal for (R-Y) output signal for (B-Y) output signal for Y ground for analog section positive analog supply voltage input signal for (R-Y) input signal for (B-Y) input signal for Y decoupling capacitor for internal reference voltage Fig.2 Pin configuration.
handbook, halfpage CLMY
SAA4981
1 2 3 4 5 6
24 BGREF 23 YIN 22 (B-Y)IN 21 (R-Y)IN 20 VCCA
CLMBY CLMRY SUB CLAOUT HREF VEED VCCD CTRL1
SAA4981
7 8 9
19 VEEA 18 YOUT 17 (B-Y)OUT 16 (R-Y)OUT 15 YSIDE 14 BYSIDE 13 RYSIDE
CTRL2 10 CTRL3 11 TEST 12
MHA276
1995 Oct 05
4
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
FUNCTIONAL DESCRIPTION Applicable video standards The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reduced video bandwidth above 5 MHz. Clamping circuit The clamping circuits clamp the video input signals Y, (B-Y) and (R-Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories. Internal pre filters Before the signals are sampled in the time discrete and amplitude continuous area, low-pass filtering is necessary to avoid any aliasing. Even if the inputs have already been low-pass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz). SC line memories After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 43. The clocks and the horizontal starting pulses for the SC line memories are fed from the controller. Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with 13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz. The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters. Clamp reference
SAA4981
Output multiplexer MUX Y, MUX (B-Y) and MUX (R-Y) The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching. The input signals of the multiplexers for one component [Y, (B-Y) or (R-Y)] are as follows: * The output signal of the post filter * The uncompressed signal after the input clamping * The clamping reference signal * The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE. The horizontal separation circuit The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the horizontal separation circuit. It is also possible to use the positive edge of the burst key of a sandcastle signal. 54 MHz horizontal PLL The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHz clock and the 18 MHz clock are line locked.
Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories. Four external capacitors at the pins CLMY, CLMBY, CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages. A black level reference signal is available at CLAOUT.
1995 Oct 05
5
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
Controller The controller generates the clocks and the horizontal start signals for the SC line memories and, also, the control signals for the output multiplexers. The timing for the start reading signal for three different screen positions (left, centre and right) and the control signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass via the SC line memories and a bypass not via the SC line memories is available. When the signals do not pass the line memories, the frequency response is not affected by the si-function. The compression and bypass mode via the line memories is delayed by one line with respect to the bypass mode not via the line memory. The 16 : 9 compressor is controlled via the control signals CTRL1, CTRL2 and CTRL3 (see Table 1). The test input must be LOW level. Table 1 Functions of the control signals FUNCTION bypass (through the line memories) compression, left position compression, centre position compression, right position bypass (not through the line memories) Signals for the side panels
SAA4981
The luminance and chrominance of the side panels is determined by the external signals YSIDE, BYSIDE and RYSIDE. This external generated side panel signal can be referenced to the internal black level reference signal via the output CLAOUT (pin 5). Horizontal timing (see Fig.3) The horizontal timing refers to the positive edge of the input HREF signal. The following timing parameters are valid for a horizontal frequency of 15.625 kHz. Input clamping typically starts at tA = 1.55 s and ends at tB = 3.78 s.
CTRL1 CTRL2 CTRL3 LOW LOW HIGH HIGH LOW LOW HIGH LOW HIGH LOW LOW LOW LOW LOW HIGH
Internal post filters The output signals of the SC line memories have to be filtered with three 6.7 MHz low-pass filters to eliminate the high frequencies caused by the time discrete signal processing. The cut-off frequency of 6.7 MHz is necessary because, as a result of the 34 compression factor, the frequencies are shifted to a higher frequency band with the inverse compression factor (e.g. 5 MHz compression 6.67 MHz). Due to the common bandwidth requirements for all three outputs of the SC line memories the same transfer function for the filters can be used. Remark: These filters do not provide an si-correction. This means that an input signal with a frequency of 5 MHz will be damped by 2.1 dB at the output if the signal passes an SC line memory.
1995 Oct 05
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Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
handbook, full pagewidth
HREF 64 s
1.5 s 1.5 s
(2) (2) (1)
sampled video 49 s (used for compression) 6.3 s 52 s 36.75 s side panel compressed video (centre position) side panel
side panel
compressed video (right position)
compressed video (left position)
side panel
bypassed video (bypass via the Line Memories)
(2) (2)
bypassed video
(1)
(full bypass not through the Line Memories)
MHA278
(1) Nominal timing for a 52 s active video signal to generate a centred compressed video signal. (2) Worst case picture position for a 52 s active video signal to generate no visible blanking between side panels and compressed video.
Fig.3 Horizontal timing.
1995 Oct 05
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Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
handbook, full pagewidth
CVBS Y/C
COLOUR DECODER TDA4650 OR TDA4655/7 AND TDA4665 sync ASC
Y -(B-Y) -(R-Y) 3
PICTURE SIGNAL IMPROVEMENT TDA4670/1
Y -(B-Y) -(R-Y) 3
16:9 COMPRESSOR SAA4981
YOUT -(B-Y)OUT -(R-Y)OUT 3
VIDEO PROCESSOR TDA4680/7 TDA4780
R G B
3 SYNC TDA2579B sandcastle 1 CTRL
1
3 SIDE
1
MHA279
Fig.4 Receiver for 16 : 9, 50 Hz and 15.625 kHz with 16 : 9 compressor.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Vn V6 Ptot Tstg Tamb Ves PARAMETER voltage on any pin (except pin 6 HREF) input voltage at pin 6 total power dissipation storage temperature operating ambient temperature electrostatic handling for all pins note 1 note 2 Notes 1. Equivalent to discharging a 200 pF capacitor via a 0 series resistor. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. QUALITY SPECIFICATION In accordance with UZW-B0/FQ-0601. ESD classification A. CONDITIONS MIN. VEEA - 0.5 VEED - 0.5 -0.5 - -25 -20 -500 -4000 MAX. VCCA + 0.5 VCCD + 0.5 +6.5 0.5 +150 +70 +500 +4000 V V V W C C V V UNIT
1995 Oct 05
8
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
CHARACTERISTICS VCCA = VCCD = 5 V; Tamb = 25 C; fHREF = 15.625 kHz; substrate connected to VEED; YSIDE, BYSIDE and RYSIDE are connected to CLAOUT; all voltages are referenced to VEEA = 0 V; input signal EBU colour bar 100/0/75/0 (CCIR recommended 471-1), Y = 0.32 V (p-p), (B-Y) = 1.33 V (p-p), (R-Y) = 1.05 V (p-p); source impedance Zis = 300 ; coupling capacitor Ck = 2.2 nF; output loads connected to ground RL = 1 M, CL = 20 pF; measured in Fig.5; test input pin 12 has to be connected to VEED; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply (pins 20, 19, 8, 7 and 4); note 1 VCCA ICCA VCCD ICCD analog supply voltage analog supply current digital supply voltage digital supply current 4.75 35 4.75 1 5.0 50 5 9 5.5 65 5.5 14 V mA V mA
Video inputs (pins 23, 22 and 21) Y ViY(p-p) CI(Y) ILI(Y) RiY(cl) (B-Y) Vi(B-Y)(p-p) CI(B-Y) ILI(B-Y) RI(B-Y)(cl) (R-Y) Vi(R-Y)(p-p) CI(R-Y) ILI(R-Y)(cl) RI(R-Y)(cl) Vi(top) ILI(HREF) CI(HREF) Vslice fi tW SHREF Vi(side) CI(side) ILI(side) input voltage (peak-to-peak value) input capacitance input leakage current between clamping input resistance during clamping active video - - - - 1.05 - - 2 - - - 0.75 15.6 - - - - - 1.5 10 0.1 5 V pF A k input voltage (peak-to-peak value) input capacitance input leakage current between clamping input resistance during clamping active video - - - - 1.33 - - 2 1.9 10 0.1 5 V pF A k input voltage (peak-to-peak value) input capacitance input leakage current between clamping input resistance during clamping active video - - - - 0.32 - - 2 0.45 10 0.1 5 V pF A k
HREF input (pin 6) input voltage of the top pulse input leakage current input capacitance slicing level below top pulse input frequency pulse width steepness 0.5 V under top 3.0 - - 0.5 14.0 1 400 6.5 10 10 1.0 17.2 - - V A pF V kHz s mV/ns
Side panel inputs (pins 15, 14 and 13) input voltage input capacitance input leakage current 0.5 - - 2.5 10 0.1 V pF A
1995 Oct 05
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Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - -
MAX. - 1.5 10 1
UNIT
Control inputs/outputs (pins 9, 10 and 11) VIH VIL CIctr ILIctr Vo5 RL CL CDL VoCDL CBGREF VoBGREF HIGH level input voltage LOW level input voltage input capacitance input leakage current 3.5 - - - V V pF A
Clamping reference output (pin 5) output voltage load resistor load capacitor 1.3 10 - - 1.3 - 1.1 1.45 - - 1.6 - 30 - 1.6 - 1.4 V k pF
External capacitors (pins 1, 2 and 3) value for capacitor output voltage 100 1.45 nF V
External capacitor (pin 24) value for capacitor output voltage 100 1.25 nF V
Video output signals (pins 18, 17 and 16) YOUT RO(Y) VoY(p-p) S/N output resistance output voltage (peak-to-peak value) signal-to-noise ratio 0.32 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz fclk < 5 MHz fi = 1 MHz - - 52 - 0.32 - 100 0.5 - V dB
FPN(p-p) ctY |td| td
fixed pattern noise peak-to-peak referenced to 0.32 V (p-p) video crosstalk between different inputs delay between different outputs jitter in output signal referenced to HREF input signal
42 40 - -
- - - -
- - 30 10
dB dB ns ns
Bypass not via the SC line memories
GY1 GY2 frequency response frequency response fripple = 0 to 4 MHz attenuation at 5 MHz compared to 1 MHz -0.5 0 - - +0.5 -2 dB dB
Bypass via the SC line memories; note 2
GY3 GY4 GY5 GY6 GY7 YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency fi = 1 MHz fi = 2 MHz fi = 3 MHz fi = 4 MHz fi = 5 MHz -1.1 -1.3 -1.7 -2.3 -3.1 - - - - - +0.9 +0.7 +0.3 -0.3 -1.1 dB dB dB dB dB
1995 Oct 05
10
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
SYMBOL
PARAMETER
CONDITIONS
MIN. -1 -1 -2 -3 -4 -6 20 32 42 20 32 40 - -
TYP. - - - - - - - - - - - - - 1.33 -
MAX.
UNIT
Compressed video; note 2
GY8 GY9 GY10 GY11 GY12 GY13 AYpre YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency pre filter stop-band characteristic, damping factor for input signals fi = 1 MHz; fo = 1.3 MHz fi = 2 MHz; fo = 2.7 MHz fi = 3 MHz; fo = 4 MHz fi = 3.75 MHz; fo = 5 MHz fi = 4 MHz; fo = 5.3 MHz fi = 5 MHz; fo = 6.67 MHz fi > 10 MHz fi > 20 MHz fi > 100 MHz AYpost post filter stop-band characteristic, damping factor for input signals fi > 14 MHz fi > 20 MHz fi > 100 MHz (B-Y)OUT RO(U) VoU(p-p) S/N output resistance output voltage (peak-to-peak value) signal-to-noise ratio 1.33 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz fclk < 5 MHz fi = 1 MHz 100 2.1 - V dB +1 +1 0 -1 -1 -1 - - - - - - dB dB dB dB dB dB dB dB dB dB dB dB
54
FPN(p-p) ctU |td| td
fixed pattern noise peak-to-peak referenced to 1.33 V (p-p) video crosstalk between different inputs delay between different outputs jitter in output signal to input HREF signal
42 40 - -
- - - -
- - 30 10
dB dB ns ns
Bypass not via the SC line memories
GU1 GU2 frequency response frequency response fripple = 0 to 4 MHz attenuation at 5 MHz compared to 1 MHz -0.5 0 - - +0.5 -2 dB dB
Bypass via the SC line memories; note 2
GU3 GU4 GU5 GU6 GU7 (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency fi = 1 MHz fi = 2 MHz fi = 3 MHz fi = 4 MHz fi = 5 MHz -1.1 -1.3 -1.7 -2.3 -3.1 - - - - - +0.9 +0.7 +0.3 -0.3 -1.1 dB dB dB dB dB
1995 Oct 05
11
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
SYMBOL
PARAMETER
CONDITIONS
MIN. -1 -1 -2 -3 -4 -6 20 32 42 20 32 40 - -
TYP. - - - - - - - - - - - - - 1.05 -
MAX.
UNIT
Compressed video; note 2
GU8 GU9 GU10 GU11 GU12 GU13 AUpre (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency (B-Y)OUT/(B-Y)IN at input frequency pre filter stop-band characteristic, damping factor for input signals fi = 1 MHz; fo = 1.3 MHz fi = 2 MHz; fo = 2.7 MHz fi = 3 MHz; fo = 4 MHz fi = 3.75 MHz; fo = 5 MHz fi = 4 MHz; fo = 5.3 MHz fi = 5 MHz; fo = 6.67 MHz fi > 10 MHz fi > 20 MHz fi > 100 MHz AUpost post filter stop-band characteristic, damping factor for input signals fi > 14 MHz fi > 20 MHz fi > 100 MHz (R-Y)OUT RO(V) VoV S/N output resistance output voltage (peak-to-peak value) signal-to-noise ratio 1.05 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz fclock < 5 MHz fi = 1 MHz 100 1.7 - V dB +1 +1 0 -1 -1 -1 - - - - - - dB dB dB dB dB dB dB dB dB dB dB dB
52
FPN(p-p) ctV |td| td
fixed pattern noise peak-to-peak referenced to 1.05 V (p-p) video crosstalk between different inputs delay between different outputs jitter in output signal to input HREF signal
40 40 - -
- - - -
- - 30 10
dB dB ns ns
Bypass not via the SC line memories
GV1 GV2 frequency response frequency response fripple = 0 to 4 MHz attenuation at 5 MHz compared to 1 MHz -0.5 0 - - +0.5 -2 dB dB
Bypass via the SC line memories; note 2
GV3 GV4 GV5 GV6 GV7 (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency fi = 1 MHz fi = 2 MHz fi = 3 MHz fi = 4 MHz fi = 5 MHz -1.1 -1.3 -1.7 -2.3 -3.1 - - - - - +0.9 +0.7 +0.3 -0.3 -1.1 dB dB dB dB dB
1995 Oct 05
12
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
SYMBOL
PARAMETER
CONDITIONS
MIN. -1 -1 -2 -3 -4 -6 20 32 42 20 32 40
TYP. - - - - - - - - - - - -
MAX.
UNIT
Compressed video; note 2
GV8 GV9 GV10 GV11 GV12 GV13 AVpre (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency (R-Y)OUT/(R-Y)IN at input frequency pre filter stop-band characteristic, damping factor for input signals fi = 1 MHz; fo = 1.3 MHz fi = 2 MHz; fo = 2.7 MHz fi = 3 MHz; fo = 4 MHz fi = 3.75 MHz; fo = 5 MHz fi = 4 MHz; fo = 5.3 MHz fi = 5 MHz; fo = 6.67 MHz fi > 10 MHz fi > 20 MHz fi > 100 MHz AVpost post filter stop-band characteristic, damping factor for input signals fi > 14 MHz fi > 20 MHz fi > 100 MHz Video outputs YOUT, (B-Y)OUT and (R-Y)OUT RATIO OF OUTPUT AMPLITUDES FOR EQUAL INPUT SIGNALS FOR Y, (B-Y) AND (R-Y) VoY/VoU VoY/VoV VoU/VoV Notes 1. V1 = VCCA - VCCD 300 mV; V2 = VEED - VEEA 300 mV with VEED = SUB (latch-up prevention). 2. This frequency response includes the si-attenuation as a result of the time discrete signal processing. An si-correction is not performed. YOUT/(B-Y)OUT YOUT/(R-Y)OUT (B-Y)OUT/(R-Y)OUT VI = 0.32 V (p-p); fi 1 MHz -0.4 VI = 0.32 V (p-p); fi 1 MHz -0.4 VI = 1.33 V (p-p) -0.4 - - - +0.4 +0.4 +0.4 dB dB dB +1 +1 0 -1 -1 -1 - - - - - - dB dB dB dB dB dB dB dB dB dB dB dB
1995 Oct 05
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Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
APPLICATION INFORMATION
SAA4981
ook, full pagewidth
+5V 47 F
ferrit pearl
10 nF 47 F VEEA
video signal inputs VEEA 100 nF 2.2 nF 24 23 2.2 nF 2.2 nF 22
2.2
10 nF 47 F
video signal outputs
CLAOUT (1)
10 nF 21 20 19 18 17 16 15 14 13
SAA4981
1 100 nF
2 100 nF
3 100 nF
4 (2)
5
6 VEED
7
8 2.2
9
10
11
12
10 nF 15
VEEA VEEA VEEA VEED 5.6 ferrit pearl line reference input clamp reference voltage output 47 F VEEA +5V control inputs see Table 1
VEED
10 nF
MHA280
(1) Connected to CLAOUT for black side panels. (2) Substrate (pin 4) has to be connected to VEED. VEEA and VEED. Substrates have to be separated as much as possible.
Fig.5 Application diagram.
1995 Oct 05
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Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
PACKAGE OUTLINES DIP24: plastic dual in-line package; 24 leads (600 mil)
SAA4981
SOT101-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 24 13 MH wM (e 1)
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-23
1995 Oct 05
15
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SAA4981
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1995 Oct 05
16
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
SAA4981
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Oct 05
17
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4981
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Oct 05
18
Philips Semiconductors
Preliminary specification
Monolithic integrated 16 : 9 compressor
NOTES
SAA4981
1995 Oct 05
19
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD44 (c) Philips Electronics N.V. 1995 Oct 05
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/02/pp20 Document order number: Date of release: 1995 Oct 05 9397 750 00346

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